Abstract
This paper presents a CAD tool, SystSim, to ease the design of systolic systems. Given a high-level, functional description of processors, and a high-level description of their interconnection, SystSim will perform simulations and provide graphical output. SystSim will also perform transformations such as retiming, which eases use of the methodology of Leiserson and Saxe of designing a system with broadcasting and then obtaining a systolic system through retiming.
| Original language | American English |
|---|---|
| Journal | Computer Science: Faculty Publications and Other Works |
| Issue number | Technical Report EE-TR-93-027 |
| State | Published - Mar 26 1993 |
Disciplines
- Computer and Systems Architecture
- Computer Sciences
- Hardware Systems
- VLSI and Circuits, Embedded and Hardware Systems